module Add_SysEx(
	// input 					add_flag,
	input 	[31:0] 			in_data0,
	input 	[31:0]			in_data1,

	output  [31:0] 			out_data
);

reg 	[31:0] 			out_data_reg;

// wire 	[31:0]			add_flag;
// assign add_flag = in_data1[32];
assign out_data = out_data_reg;

always @(*) begin
	// out_data_reg = in_data0 + (in_data1<<2);
	out_data_reg <= in_data1;
end

endmodule 